Technological advances in semiconductor integrated circuit processing allows IC manufacturers to build IC chips with higher integration densities and smaller design rules leading to increasing complex IC designs having a large number of cells that require complex connections between the cells. The rapid densification of VLSI (Very Large Scale Integrated) circuit devices, associated with high speed circuit performance, and relatively short time-to-market, has driven the need to rapidly characterize and diagnose complex integrated circuit designs early in the product cycle. The most common method of designing logic circuits for placement on IC chips is done with the use of computer systems and software that use computer-aided design (CAD) tools that allow for an efficient design, checking and testing of VLSI circuits using logic synthesis and physical design tools.
In general, a logic synthesis tool takes as input a functional description of a logic circuit and converts it into a technology level description. During logic synthesis, a high-level electronic circuit design is converted into a list of books or cells and their interconnections, which is referred to as a “netlist.” A “book” (or cell) refers to an identifiable primitive function (i.e., “cell”) (included in a technology library) that includes a pre-designed circuit for performing a certain Boolean function, together with relevant information about the circuit. Following logic synthesis stage, a physical design tool is used for “placement” where the books/cells in the netlist are placed to a physical location on the chip, and “routing” where each net in the netlist is assigned a set of wire segments which implement the interconnections defined by the net. The output of the physical design stage results in a physical layout of the chipstage with a set layout level representation that a chip foundry can use to actually build the chip.
The entire functionality of a digital VLSI IC is controlled and synchronized by various clocks that run through the system. In this regard, the design and implementation of the clocking structure is critical step in the design of a VLSI chip. With the increased clock speeds, process densities and logic complexities, IC designers a faced with significant challenges to meet timing constraints such as cycle-time overlap violations associated with launch and capture clocks in a master-slave latch clocking system.
FIG. 1 is a schematic block diagram of a master-slave latch logic circuit in which wiring methods according to exemplary embodiments of the invention may be implemented for launch and capture clock wires to minimize cycle-time violations. In FIG. 1, a master-slave latch circuit (10) includes a first master/slave latch (10_1) and a second master/slave latch (10_2), each having a master latch L1 and slave latch L2. A logic circuit (11) is connected between the first and second master/slave latches (10_1) and (10_2). A typical clock connection for the master-slave latch circuit (10) comprises three main clock lines, a capture clock C line, a launch clock B line, and a test clock A line. The master latches L1 are controlled by a clock signal C, wherein the assertion of C causes master latches L1 to capture data input to the respective latch (10_1) and (10_2). The slave latches L2 are controlled by the clock signal B, wherein assertion of B signal causes slave latches L2 to launch the data input captured during a previous C pulse to the latch output. The clock signals B and C are complements of each other and the A clock is a clock signal that is used for test purposes. The A clock signal has a significantly lower frequency compared to the B and C clocks and is inactive during the functional mode of the chip.
In order to properly operate in a launch/capture mode, the launch and capture clocks must be properly synchronized otherwise timing errors due to cycle-time overlap violations can significantly impact performance. FIGS. 2A-2D are timing diagrams that illustrate cycle-time issues with regard to synchronization of launch and capture clocks in a master-slave latch circuit of FIG. 1. FIG. 2A illustrates an exemplary B (launch) clock signal that is input to the slave latches L2 and FIGS. 2B-2C illustrate C (capture) clock signals in various timing relationships with the B clock signal in FIG. 2A. The timing diagrams of FIGS. 2A and 2B illustrate proper synchronization between the launch B clock signal and the capture C clock signal. As shown in FIG. 2A, a time period T1 represents a clock cycle “n” which starts at the leading edge of the launch clock (start-of-cycle or soc(n)) and ends at the trailing edge of the subsequent capture clock (end-of-cycle or eoc(n)). In FIG. 2B, the time period T2 (or “mid-cycle un-overlap”) denotes a time buffer between the active periods of the launch and capture clocks within the cycle T1. The mid-cycle un-overlap condition as depicted in the timing diagrams of FIGS. 2A and 2B illustrates proper synchronization.
The timing between the launch and capture clocks in FIGS. 2A and 2C illustrate a “mid-cycle overlap violation” where the active periods of the capture and release clocks overlap in a master-slave latch. In FIG. 2C, the time period T3 (or “mid-cycle overlap violation”) denotes a time overlap between the active periods of the launch and capture clocks within the cycle T1 wherein the capture and launch clocks for a stage are active at the same time. This timing violation leads to an unstable flush-through state for the latch resulting in loss of valid data. In this condition, the capture and launch clocks for a stage active at the same time and the data in that stage will have a flush-through effect which may lead to the wrong stage of the data being launched and being captured at the subsequent stage.
The timing between the launch and capture clocks in FIGS. 2A and 2D illustrate a “cycle-to-cycle overlap violation.” A cycle-to-cycle overlap violation occurs when the capture clock for one stage is not yet at the end of cycle state when the launch clock for the subsequent stage becomes active. In FIGS. 2A and 2D, a cycle-to-cycle overlap violation is shown where the C clock of stage n (FIG. 2D) is active along with the B clock of stage n+1 (FIG. 2A).
With higher clock frequencies and process densities, this synchronization is often compromised, if not addressed specifically during the IC design. In general, the cycle time violations described above are commonly caused by variation in propagation delay between the B and C clocks signals, which propagation delay can be caused by various reasons. In the logic design stage, cycle time violations can be addressed by using the same number of levels and the same latency books for distributing both the launch and capture clocks. However, at the physical design level, cycle time violations are more difficult to address with regard to PD scheduling since cycle time violations are usually detected usually after the clocks are wired and timed late into the physical design cycle. Also complexities arise for a PD solution because of process variation in manufacturing causes differences in latency values for books that are defined to have the same latency when the books are placed in different locations on the chip.
One way to maintain synchronization between capture and launch clocks due to silicon process variation is to generate the clock signals from a single source with the necessary time buffer between them and distribute the signals throughout the design with the same propagation delay so that they remain synchronized using Local Clock Buffers (LCBs) and multi IO post LCB repeaters. Using the LCB methodology the launch and capture clocks are generated from the same oscillator signal and distributed using multiple IO post LCB clock buffers. FIG. 3A schematically illustrates a Local Clock Buffer (LCB) circuit (30) that generates B and C clock signals with the appropriated mid-cycle un-overlap time based on a single input clock signal OSC. The test clock A signal is generated by the LCB (30) from an ACLK input signal. FIG. 3B illustrates a post LCB repeater circuit (31) which includes multiple buffers within a single book. The repeater (31) is designed so that the distribution of the three clocks A, B and C are completely synchronized with each other. The LCB (30) and repeater (31) clocking system maintains clock synchronization by minimizing propagation delay caused by silicon process variation due to the buffers. The process variation involved with the silicon in the buffers is minimized since the buffers are physically disposed in next to each other. In short, LCB methodology eliminates the possible lack of synchronization of the B and C clocks due to silicon process variation.
Although LCB distribution frameworks address delay difference due to silicon variation, for higher frequency designs, synchronization of the B and C clock signals may be compromised due to variation in propagation delay in the metal wires used to connect the pins between the LCBs and repeater stages. Balanced wiring is one solution that can be used to ensure that propagation delay due to the wires is maintained the same. However, balanced wiring does not address variation in propagation delay in wires caused by metal process variation when the wire segments between the B and C clocks are not physically located in proximity to each other. Indeed, if the capture/launch clock wire pairs have the same length but are not physically located near each other, metal process variation (e.g., variation in line resistance, profile, etc.) between the wire pairs may exist, causing different propagation delays over the B and C wires.
One way to combat this problem is to route B and C clock wire pairs in parallel to each other with a minimum distance between them. But this results in noise interference between the B and C clocks. Indeed, even though B and C clocks may be considered as exact compliments from a high level design standpoint, the B and C clocks are commonly misaligned by some time margin for the purpose of achieving the cycle-to-cycle un-overlap (as discussed above with reference to FIGS. 2A and 2B. Therefore, running the wires in parallel right next to each other makes them susceptible to coupled noise interference between each other and will degrade the signal integrity.
In view of the above, no effective solution exists for addressing and eliminating cycle time overlap violations upfront in the design cycle for VSLI designs. As such, mid-cycle and cycle-to-cycle overlap problems typically arise as timing violations at the end of the physical design cycle where the full chip is wired thereby forcing the physical designer to deal with such timing violation on a selective manual basis, The late stage wiring modification becomes an extremely sensitive issue to deal with from a timing closure standpoint at such late stage of design as any changes to the clock wires can have a ripple effect on the timing for the rest of the design and all these changes can have a telling effect on the design schedule. Therefore, a method is needed to address these potential timing issues earlier in the design cycle